When digital data are transmitted over a signal channel, they are known to suffer from intersymbol interference which is dependent on the particular channel response and the input data pattern. Examples of digital data transmission channels are microwave and satellite transmission channels, telephone communication lines, or magnetic recording/reproduction of digital data. In the above described type of channels the amplitude response in time domain to a single pulse has a ringing characteristic, which in turn results in superposition of otherwise unrelated, distinct input pulses. The foregoing undesirable effect causes amplitude variation, in turn causing incorrect amplitude detection at sampling time, and thus errors in the detected data bits.
As it is well known in the art, the signal received from a transmission channel is sampled at predetermined sampling intervals. The detected amplitude of each sample is digitized and compared to a threshold. When the digitized amplitude value exceeds the threshold, it is detected as a binary one, and when it is below the threshold it is detected as a binary zero. However, due to intersymbol interference, the sampled waveform represents a superposition of pulses. Therefore, for a given channel having a know amplitude response, the amplitude at each sampling time varies with the particular data pattern being decoded. Decision data decoders have been developed to correct for the intersymbol interference as follows. These known decoders store a predetermined number of previously decoded bit values, generally referred to as decisions, made by the decoder. These stored decisions are fed back to the decoder logic, which then makes the next decision about a particular sample value considering the previous decision values and particular channel characteristics. More particularly, the known decision feedback decoders provide a correction value for each detected bit, and adjust the threshold value accordingly, thereby compensating for the intersymbol interference.
The operation speed of existing decision feedback decoders is limited to that attainable by the logic circuitry which makes the decisions. These known decision feedback decoders are capable of making one decision, that is to decode one sample of the transmitted signal, within one clock cycle.
The decision feedback decoder in accordance with the preferred embodiment of the invention has two parallel signal paths. The first and second path both receive sequentially an input data stream, but only every other data bit of the stream is input into a first logic circuit in the first path to be decoded thereby. The first logic circuit makes a decision about the value of the received bit by comparing that value to a threshold. The first path has first storage means for storing a predetermined number of previous decisions, that is bit values previously decoded by the first logic circuit. The first logic circuit adjusts the threshold before making any new decision, on the basis of previously made stored decision values and the known channel response. The second signal path has a second logic circuit which receives the same input data bit simultaneously with the first logic circuit, and it receives a second, subsequent data bit. The second data path has a second storage means for storing a predetermined number of previous decisions made by the second logic circuit. Both logic circuits receive the stored decisions which are fed back from both the first and second storage means. The second logic circuit outputs every second decision made thereby, which decisions determine the values of input data bits alternating with those received by the first logic circuit.
In operation, the first logic circuit, which receives every other bit of the input bit sequence, makes a first decision about a particular input bit within one clock cycle, and it outputs that decision. The second logic circuit, which receives simultaneously two subsequent input bits, makes two subsequent decisions within the same clock cycle, and it outputs the second made decision. It utilizes the first made decision within that clock cycle internally for providing the second decision. It is a particular advantage of the invention that the second logic circuit provides two subsequent decisions within the same clock cycle, and that it considers the first made decision as a previous decision during the second decision making process. The thusly detected data bits are taken alternatively from the respective outputs of the first and second logic circuit, where each first decision within a clock cycle is taken from the first logic circuit, and each second decision made within the same clock cycle is taken from the second logic circuit. The threshold which is utilized in the decision making process is continually adjusted for each decision, depending on the previous decision values and particular channel response characteristics.
In the preferred embodiment of the invention the second logic circuit is implemented by a relatively large capacity RAM, and the first logic circuit by a relatively small capacity RAM. For example the capacity of the second logic circuit RAM is 16 Kbits, and of the first logic circuit RAM is 512 bits. The input signal from the transmission line is a playback signal which is obtained by recording and subsequently playing back a digital signal from a magnetic medium. The first signal path has a first analog-to-digital (A/D) converter which receives the playback signal and samples it at a first clock signal. The second signal path has a second A/D converter which samples the playback signal at a second clock signal, which is delayed with respect to the first clock signal by one half clock cycle. Thus each A/D converter outputs digitized samples at one half of the combined sampling rate at which the resulting subsequent samples in both signal paths are obtained. Alternatively, the logic circuits may be implemented by combinational logic, where the second logic circuit will have approximately twice the number of logic elements utilized by the first logic circuit.